MIPS 架构和 ARM 架构有什么样异同点?在CPU IP授权上ARM 是怎样战胜MIPS的
------------------------------异-----------------------------------
^
MIPS架构中指令定长[①],ARM架构不是[②]。MIPS架构中有指令延迟执行槽[③],ARM架构下没有[③]。这个设计是为了更好的装满流水线[④]。
于是就这②点谈谈(?)
第①点:较短的opcode提供整体更佳的编码密度
摘自:第②点:The goal of a pipelined architecture is to complete an instruction every clock cycle. To maintain this rate, the pipeline must be full of instructions at all times. The branch delay slot is a side effect of pipelined architectures due to the branch hazard, i.e. the fact that the branch would not be resolved until the instruction has worked its way through the pipeline. A simple design would insert stalls into the pipeline after a branch instruction until the new branch target address is computed and loaded into the program counter.
摘自
------------------------------同-----------------------------------
^
总的来说,ARM和MIPS都是IBM提出了RISC的概念并将它推广出来之后,受此影响作出的设计;它们都有不少RISC的影子。RISC风格,总的来说,会有更多的寄存器,内存访问方式会相对受限,指令数常常只有②、③⑩个。(来源请求)
------------------------------引用内容---------------------------
^
①.MIPS architecture
Designer -- MIPS Technologies, Inc.
Bits -- ⑥④-bit (③②→⑥④)
Introduced -- ①⑨⑧①
Design -- RISC
Type -- Register-Register
Encoding -- Fixed②.ARM架構
较新的ARM处理器有①种①⑥-bit指令模式,叫做Thumb,也许跟每个条件式运行指令均耗用④位的情形有关。在Thumb模式下,较小的opcode有更少的功能性。例如,只有分支可以是条件式的,且许多opcode无法访问所有CPU的暂存器。然而,较短的opcode提供整体更佳的编码密度(注:意指代码在存储器中占的空间),即使有些运算需要更多的指令。特别在存储器端口或总线宽度限制在③②以下的情形时,更短的Thumb opcode能更有效地使用有限的存储器带宽,因而提供比③②位代码更佳的性能。③.Delay slot
MIPS, PA-RISC, ETRAX CRIS, SuperH, and SPARC are RISC architectures that each have a single branch delay slot; PowerPC, ARM, and the more recently designed Alpha do not have any. ④.Delay slot
The goal of a pipelined architecture is to complete an instruction every clock cycle. To maintain this rate, the pipeline must be full of instructions at all times. The branch delay slot is a side effect of pipelined architectures due to the branch hazard, i.e. the fact that the branch would not be resolved until the instruction has worked its way through the pipeline. A simple design would insert stalls into the pipeline after a branch instruction until the new branch target address is computed and loaded into the program counter.
早期ARM的优势就是面积小,其第②大股东是苹果,第①个客户是苹果的PDA牛顿。牛顿失败后,被苹果无情抛弃的ARM苦苦挣扎了很多年,被TI、LSI等公司小规模采用完全是因为比MIPS便宜。
⑨⓪年代手机开始兴起,为了击败空前强大的摩托罗拉,诺基亚和TI合作,希望开发出首款适用②G网络的通讯芯片。TI先后介绍了自家的MCU核心、标准的MIPS核心、以及标准的ARM核心。诺基亚的思路是选择①款不被大佬掌控的CPU,这样便于在未来的改进上施加影响,显然只有苦逼的ARM符合要求。于是傍着诺基亚的巨型航母,ARM就赶上了移动市场的大潮。之后ARM不断在低功耗、Java加速、单指令多数据、代码压缩等方面发力,彻底满足了诺基亚的需求,也拉开了和MIPS的距离。
另①个击败MIPS的因素是授权方式,MIPS收取IP授权要比指令集授权更贵,而且允许添加指令,这就使得大佬们纷纷自行设计MIPS核心、添加指令、发布开发工具,碎片化严重。而ARM反其道行之,指令集授权远远比IP授权要贵,控制了碎片化。当时ARM还极有眼光的设计了全世界最好用、最便宜的USB调试工具,吸引了①批码农,从而构建了巨大的ARM开源软件库。
- 5星
- 4星
- 3星
- 2星
- 1星
- 暂无评论信息
